Pico Systems

Universal PWM Controller Register Definition

Address                 Read                       Write
 0    00           Encoder 0 low byte        Assembly Register low byte
 1    01           Encoder 0 mid byte        Assembly Register mid byte
 2    02           Encoder 0 hi  byte        Assembly Register hi  byte
 3    03           Encoder 1 low byte        Encoder Control Register
 4    04           Encoder 1 mid byte        Timer config Register
 5    05           Encoder 1 hi  byte        
 6    06           Encoder 2 low byte
 7    07           Encoder 2 mid byte
 8    08           Encoder 2 hi  byte
 9    09           Encoder 3 low byte
10    0A           Encoder 3 mid byte
11    0B           Encoder 3 hi  byte
12    0C           Index Sense Register
13    0D           Digital Inputs 0-7        Index Preset Register
14    0E           Digital Inputs 8-14,Estop
15    0F           Module ID code 0x52       value to DAC via P8
16    10                                     Assembly register low byte
17    11                                     Assembly Register hi  byte, set Axis 0 Duty Cycle
18    12                                     Assembly register low byte
19    13                                     Assembly Register hi  byte, set Axis 1 Duty Cycle
20    14                                     Assembly register low byte
21    15                                     Assembly Register hi  byte, set Axis 2 Duty Cycle
22    16                                     Assembly register low byte
23    17                                     Assembly Register hi  byte, set Axis 3 Duty Cycle
24    18
25    19
26    1A
27    1B
28    1C                                     PWM Generator Control Register
29    1D				     Load PWM Frequency Register (lo byte)
30    1E				     Load PWM Frequency Register (hi byte)
31    1F	                             set/clear Estop, SSR outputs

Encoder Count Registers

The encoder count registers are a 24-bit straight binary up/down counter broken into three bytes. The most significant byte contains a normal, 2's complement sign. This value represents the count of edges of the quadrature waveform coming into the A and B inputs to the board from the encoders. This 24-bit value has been latched into a holding register, so there will be no mis-reading of the value due to encoder counts being received during the read of the three bytes.

Encoder Control Register

Encoder Control Register Bits :
  Bit #   7     6     5     4     3     2     1     0
  Axis #  3     2     1     0     3     2     1     0
Function  ---Load Position---     ---Index Select----

The load position bits will cause that axis's encoder counter to load the 24-bit value now in the assembly register. This bit needs to be set to a one, held for at least 2 uS, and then cleared back to zero. Multiple axes can be set at the same time, if setting all to the same value.

The Index select bit, when 1, will cause that axis's 24-bit latch to only latch the encoder count when the index pulse is sensed from the encoder. It will latch on the rising edge of the index pulse. This will also set the index sense bit in the index sense register. If the Index Select bit is 0, then the latch will latch the count every time the Intr bus signal is asserted. This will happen when the timer generates a pulse or when it is commanded by the soft latch bit in the timer register.

Index Preset Register

Index Preset Register Bits :
  Bit #   7     6     5     4     3     2     1     0
  Axis #                          3     2     1     0
Function  ---    none     ---     ---Index Preset----

The index preset bit, when set to 1, will cause that axis' 24-bit position counter to be loaded with the value contained in the encoder preset register whenever the encoder's index (Z) signal is detected.

Timer Register

Timer Register Bits :
  Bit #   7     6     5     4     3     2     1     0
Function none  none soft  master tim3  tim2  tim1  tim0
                    latch

Description of Timer Register Bits :

SoftLatch - when there is no 'master' encoder, then writing a 1 to this bit generates a software controlled latching of the encoder counts. Write a 0 after writing the 1.
Master - Setting this bit to 1 selects this Universal PWM as the master board, such that it drives the bus Intr line to cause any other encoder counters to also latch the count, and any other UPM boards to update the PWM duty cycle from the holding registers. Leaving this bit at 0 (power on default) causes the board to accept the Intr signal from other units.
TIM(3:0) These select the count down divisor from a 10 KHz clock. 1111 means don't divide, so the encoder will be latched every 100 uS (10 KHz). The counter counts up to 1111 from whatever value is entered, so a setting of 0110 (6) will go through 10 states before automatically reloading this value. Therefore, loading 6 here will make the encoders latch at a 1 KHz rate.

Index Sense Register

Index Sense Register Bits :
  Bit #   7     6     5     4     3     2     1     0
  Axis #                          3     2     1     0

The 4 LS bits are a latch for sensing of the index pulse. The axis must have the index select bit turned on in the control register, and this register must be read once (which clears it after the read) before the values are meaningful.

PWM Generator

PWM Generator : The PWM generator operates from a 10 MHz clock, and divides this by the count in a 16-bit register. (On the UPC Rev 3.1 and later, the clock is 40 MHz, rather than 10. The ID register of this board will report 0x53 or a higher digit in the 4 least significant bits) for the 40 MHz units.) A 16-bit counter starts at the value in the 16-bit PWM Frequency Register, and counts up until all bits are one. It then is reset to the value in the PWM frequency register, and starts again. At this time, if the PWM control register enable bit is a one, the PWM output goes to a logic one. While the counter is counting up, the count value is compared to the value loaded into the PWM duty cycle register. When the counter's value is greater than the value in the PWM duty cycle register, the output drops to zero.

The Assembly Register is a 24-bit register that assembles 16- and 24-bit value from 2 or 3 bytes input to the board. When the bytes have been assembled, they are automatically loaded into the multi-byte destination register. This prevents each byte from being loaded as the computer sends it, which could cause a mixture of old and new bytes to be combined. These registers are arranged so that all 8 PWM bytes can be written to in a burst, after setting the address of the first one with the IEEE-1284 nADDRSTB signal.

PWM Control Register

PWM Generator Control Register :
  Bit #   7     6     5     4     3     2     1     0
  Axis #  3     3     2     2     1     1     0     0
function run   dir   run   dir   run   dir   run   dir

The run bit enables that axis to generate PWM pulses at the programmed rate and duty cycle. The dir bit sets the direction of that axis to 1 or zero, as set by the dir bit.

Addressing the module : This board accepts an address on the 5 LS bits of the data bus during assertion of ADDRSTB on the EPP bus to select which register will be read or written. The 3 MS bits are used to select which board is addressed. The convention, at present, is to have the first universal PWM board at address 000xxxxx, and the 2nd board, if any, at 001xxxxx. Dip Switch position 10 should be ON for the first board and OFF for the second. After each data byte is transferred, the internal address counter increments. You can select the first address in the board (first addr in first board would be 00000000 ) and then read all 12 bytes of the encoder position (3 bytes x 4 axes) with 12 consecutive read byte operations, causing the DATASTB line to pulse.

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