Pico Systems

Quadrature Encoder Counter Register Definition

Address       Read                       Write
 0         Axis 0 low byte           Assembly Register low byte
 1         Axis 0 mid byte           Assembly Register mid byte
 2         Axis 0 hi  byte           Assembly Register hi  byte
 3         Axis 1 low byte           Control Register
 4         Axis 1 mid byte           Timer config Register
 5         Axis 1 hi  byte
 6         Axis 2 low byte
 7         Axis 2 mid byte
 8         Axis 2 hi  byte
 9         Axis 3 low byte
10         Axis 3 mid byte
11         Axis 3 hi  byte
12         Index Sense Register
13, 14     not used
15         Module ID code 0x11
The axis read registers are a 24-bit straight binary up/down counter broken into three bytes. The MSB contains a normal, 2's complement sign. This value represents the count of edges of the quadrature waveform coming in the A and B inputs to the board from the encoders. This 24-bit value has been latched into a holding register, so there will be no mis-reading of the value due to encoder counts being received during the read of the three bytes.

The Holding Register is a 24-bit register that assembles a 24-bit value from 3 bytes input to the board. When the 3 bytes have been assembled, they can be loaded into one of the counters through the control register.

Control Register Bits :
  Bit #   7     6     5     4     3     2     1     0
  Axis #  3     2     1     0     3     2     1     0
Function  ---Load Position---     ---Index Select----
The load position bits will cause that axis's encoder counter to load the 24-bit value now in the assembly register. This bit needs to be set to a one, and then cleared back to zero.

The Index select bit, when 1, will cause that axis's 24-bit latch to only latch the encoder count when the index pulse is sensed from the encoder. It will latch on the rising edge of the index pulse. This will also set the index sense bit in the index sense register. If the Index Select bit is 0, then the latch will latch the count every time the Intr bus signal is asserted. The master encoder counter board will assert this line every time the timer generates a pulse.

Timer Register Bits :
  Bit #   7     6     5     4     3     2     1     0
Function none  none soft  master tim3  tim2  tim1  tim0
                    latch    
Description of Timer Register Bits :

Index Sense Register Bits :
  Bit #   7     6     5     4     3     2     1     0
  Axis #                          3     2     1     0
The 4 LS bits are a latch for sensing of the index pulse. The axis must have the index select bit turned on in the control register, and this register must be read once (which clears it after the read) before the values are meaningful.

Addressing the module : This board accepts an address on the 4 LS bits of the data bus during assertion of ADDRSTB on the EPP bus to select which register will be read or written. The 4 MS bits are used to select which board is addressed. The convention, at present, is to have the first encoder counter at address 0000xxxx, and the 2nd board, if any, at 0001xxxx. After each data byte is transferred, the internal address counter increments. You can select the first address in the board (first addr in first board would be 00000000 ) and then read all 12 bytes (3 bytes x 4 axes) with 12 consecutive read data operations, causing the DATASTB line to pulse.

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