PPMC DIO

The DIO occupies a block of 4 consecutive addresses on the EPP (IEEE 1284 protocol) bus. The high 4 address bits are specified through a 4-position DIP switch marked SW1. Note that although only 4 addresses are used, 16 are made unavailable because only the high 4 bits are brought out to the address dip switch. The most significant bit (bit # 7) is switch 4, the least significant fixed address bit (bit # 4) is switch 1.

Connectors :

ST1 and ST2 are for connecting the digital inputs. ST1 has digital inputs 0 through 9, and ST2 has digital inputs 10 through 15, the fault chain, and connections for the isolated 5 V power supply. These inputs should be connected to a switch that connects the input pin to EXTGND to sense a zero at the PC parallel port. On all connectors in the drawing, Pin 1 appears at the bottom.

ST1 pins are as follows :

Pin # Signal
1 Dig. Input 0
2 Dig. Input 1
3 Dig. Input 2
4 Dig. Input 3
5 Dig. Input 4
6 Dig. Input 5
7 Dig. Input 6
8 Dig. Input 7
9 Dig. Input 8
10 Dig. Input 9

ST2 pins are as follows :
Pin # Signal
1 Dig. Input 10
2 Dig. Input 11
3 Dig. Input 12
4 Dig. Input 13
5 Dig. Input 14
6 Dig. Input 15
7 Fault Supply (+)
8 Fault Sense (-)
9 Ext Gnd
10 Ext +5 V Supply

ST3 and ST4 are for connecting the digital outputs, which are solid state relays of your choice. ST3 has digital outputs 0 through 3, and ST4 has digital outputs 4 through 7. Note that output 7 is harwired to the estop logic, so that that SSR is turned on whenever the estop flip-flop is turned off (not in e-stop). The 8 SSR outputs are completely isolated, so operation with mixed voltages (24 V AC, 120 V AC, 24 V DC) is possible.

ST3 pins are as follows :

Pin # controlling bit # Signal
1 0 SSR 1 Line
2 0 SSR 1 Load
3 1 SSR 2 Line
4 1 SSR 2 Load
5 2 SSR 3 Line
6 2 SSR 3 Load
7 3 SSR 4 Line
8 3 SSR 4 Load

ST4 pins are as follows :

Pin # controlling bit # Signal
1 4 SSR 5 Line
2 4 SSR 5 Load
3 5 SSR 6 Line
4 5 SSR 6 Load
5 6 SSR 7 Line
6 6 SSR 7 Load
7 7 SSR 8 Line
8 7 SSR 8 Load
All JP2 pins should be jumpered vertically (as the board is shown in the drawing below). This jumper field is only for reprogramming the CPLD chip U3. This jumper field is normally shunted on the PC board, so no header or jumpers are required.
Board Layout

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